Mass production of digital systems, that has led to the enormous creation of wealth, relies critically on high-quality testing tools and techniques. The more commercially successfull the design is, the more emphasis is placed on the quality of tests. This course teaches the basics of digital system testing and Design for Testability (DFT). Issues in modeling of manufacturing faults will be presented, followed by the algorithmic approach of generating tests for combinational and sequential circuits. DFT methodologies and Built-in Self-Test (BIST) presentation will concentrate on practical implementation issues. Executive summary is here, while the technical topic overview (part I) can be found here.
M. L. Bushnell and V. D. Agrawal, Essential of Electronics
Testing for Digital, Memory and Mixed-Signal Circuits, Kluwer
Academic Publishers, 2001.
K. Radecka and Z. Zilic, Verification by Error Modeling: Using Testing Methods in Hardware Verification, Kluwer
Academic Publishers, 2001.
M. Abramovici, M. A. Breuer and
A. D. Friedman,
Digital System Testing and Testable Design, IEEE
Press, 1995.
| Background: Fault Modeling, Algorithmic Background, Circuit Representation [1 week] |
| Automatic Test Pattern Generation (ATPG): Stuck-at Faults: algebraic and structural approaches; use of SAT, Bridging Faults, Delay path faults [4 weeks] |
| Testable Circuit Design: Ad hoc DFT, Observability additions, scan and standards [2 weeks] |
| Sequential Logic Testing: State-Based and Scan Techniques [2 weeks] |
| BIST: Techniques and vector generation [2 weeks] |
| Fault Tolerance: Concepts, Self-repair[1 week] |
| Presentations: [2 weeks] |