Workshop Papers
- M. Boule and Z. Zilic, "An FPGA Move Generator for the Game of Chess", TEXPO Exposition, CMC Symposium on Microelectronics Research and Development, Ottawa, Jun. 2002.
- J-F. Boland, S. Bourduas, Y. Fan, Y. Wang and Z. Zilic, "Intellectual Core Design and Verification", TEXPO Exposition, CMC Symposium on Microelectronics Research and Development, Ottawa, Jun. 2002.
- S. McCracken and Z. Zilic, "Using Reconfigurability as a Resource for Speeding up Testing and Diagnosis", Micronet R&D Annual Workshop, Aylmer, Apr. 2002.
- K. Radecka and Z. Zilic, "Transformations for Combined Vector/Formal Verification of Datapaths", Micronet R&D Annual Workshop, Aylmer, Apr. 2002.
- M. Boule, A. Chattophadyay, M-W. Chiang, S. McCracken and Z. Zilic,
MCSoC 2: A Second Generation Managed Clock System-on-a-Chip",
TEXPO Exposition, CMC Microelectronics Research and Development,
Ottawa, Jun. 2001. Honorary Mention
- Y. Danan and Z. Zilic, "HANP: A Highly Adaptive Network Processor
for FPGAs",
TEXPO Exposition, CMC Microelectronics Research and Development,
Ottawa, Jun. 2001.
-
H. Chan, I. Brynjolfson, Y. Danan, B. Polianskikh and Z. Zilic,
"MCSoC: A Research Testbed for Clock Management and Substrate Modeling",
Micronet R&D Annual Workshop,
Aylmer, Quebec, Apr. 19-20, 2001.
-
K. Radecka, Z. Zilic and K. Khordoc,
"Verification of Combinational Circuits by Simulations, SAT, ATPG and BDDs",
Micronet R&D Annual Workshop,
Aylmer, Quebec, Apr. 19-20, 2001.
-
I. Brynjolfson and Z. Zilic,
"Dynamic Clock Management for Low Power Applications",
Micronet R&D Annual Workshop,
Ottawa, Ontario, Apr. 19-20, 2000.
-
Z. Zilic and K. Radecka,
"Don't Care FDD Minimization by Interpolation",
International Workshop on Logic Synthesis, IWLS'98, Lake
Tahoe, CA., Jun 10-14, 1998.
-
Z. Zilic and Z. G. Vranesic,
"On feasible transforms for incompletely specified functions",
Proceeding of the 1997 Workshop on Post-Binary Ultra-Large Scale
Integration, Antinogish, N.S., May 1997.
-
Z. Zilic and Z. G. Vranesic,
"Application of Order to Interpolation and Learning",
Workshop "ORDAL '96", "Order and Decision Making",
Ottawa, Aug. 5 - 9, 1996.
-
Z. Zilic and Z. G. Vranesic,
"Using Decision Diagrams to Design ULMs for FPGAs",
Proceeding of the 1996 Workshop on Post-Binary Ultra-Large Scale
Integration, Santiago de Campostela, May 1996.
-
Z. Zilic, G. Lemieux, K. Loveless, S. Brown and Z. G. Vranesic,
"Designing for High Speed-Performance in CPLDs and FPGAs",
Proceeding of the Third Canadian Workshop on FPGAs, FPD 95, Montreal,
Montreal, June 1995.
-
Z. Zilic,
On Designing High-Speed Controllers Using FPGAs and PLDs , TRIO/ITRC Retreat,
Kingston, Ontario, May 1995.
-
Zeljko Zilic,
Multiple-Valued Logic in FPGAs,
First University of Toronto "Field-Programmable
Retreat", Port Stanton, Ontario, June 1993.
-
Z. Zilic and Z. G. Vranesic.
"On Retargeting with FPGA Technology",
Proceedings of the First Canadian Workshop on Field Programmable Gate Arrays,
Winnipeg, May 1993, 14-1 - 14-5.
Technical Reports
-
Z. Zilic, K. Loveless, S. Caranci, R. Grindley, M. Gusat, G. Lemieux
and N. Manjikian
Implementation of the Processor Card for the NUMAchine
Multiprocessor , Technical Report, University of Toronto,
Department of Electrical and Computer Engineering, March 1996.
-
Z. Vranesic, S. Brown, M. Stumm, S. Caranci, A. Grbic, R. Grindley,
M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, Z. Zilic,
T. Abdelrahman, B. Gamsa, P. Pereira, K. Sevcik, A. Elkateeb, S. Srbljic,
The NUMAchine Multiprocessor Technical Report, .
( postscript )
-
Z. Zilic, "Current-Mode Galois Field Circuits and Implementation of Multiple-Valued Logic Circuits",
M. A. Sc. Thesis, University of Toronto, 1993.
-
Z. Zilic and M. Molle "Modelling the Exponential Backoff Algorithm in CSMA-CD Networks",
Technical Report CSRI-279, Computer Systems Research Institute, Toronto, Oct. 1992.
-
Z. G. Vranesic, S. Zaky, C. Hamacher, A. Sanwalka and Z. Zilic: "An Implementation of the Tornet2 Local Area Network",
Technical Report, University of Toronto, Department of Electrical Engineering,
September 1991.
Book Reviews
Course Projects
These are some of the course projects done here at UofT. Pointers
are added only to
the projects whose disclosure cannot interfere with teachers'
plans. For others, please contact me.